1. Field of the Invention
The present invention relates to output buffer circuitry and, more particularly, to an output buffer circuit for converting complementary metal-oxide-semiconductor (CMOS) signal levels to emitter coupled logic (ECL) signal levels for driving the inputs of ECL gates.
2. Discussion of the Prior Art
Because of the increased speed and performance which result from ECL-based systems, the use of emitter-coupled logic in digital systems has continued to expand and is now quite common. The increased speed of ECL-based systems results from the fact that ECL gates inherently operate in a non-saturation state. Thus, the propagation delay of a typical ECL gate is low in comparison with other conventional integrated circuit transistor technologies. ECL-based systems also offer the advantages of superior analog performance and greater current drive per area. However, ECL gates typically exhibit relatively high power dissipation and a small noise margin.
On the other hand, while metal-oxide-semiconductor (MOS) circuit configurations do not typically exhibit the speed of ECL-based systems, there are a number of important advantages associated with MOS technology: MOS circuits may be designed with a high packing density that allows more circuit elements to be placed in a given chip area; thus, large, complex functions may be integrated in MOS-based systems. Simple and economical process techniques may be used for fabricating MOS integrated circuits (IC's). MOS circuits consume less power than bipolar circuits. MOS systems exhibit large noise margins and noise immunity.
In particular, complementary MOS (CMOS) circuits, which employ a symmetrical combination of n-type and p-type MOS transistors, have become extremely popular for low power dissipation applications.
Thus, it is desirable to integrate the speed of bipolar ECL logic with the practicality of MOS design for certain applications.
Mixed bipolar-MOS integrated circuit technology, commonly designated as BiMOS or BiCMOS, is well known in the art. See B. Cole, "Mixed-Process Chips are about to Hit the Big Time," Electronics, Vol. 59, No. 9, Mar. 3, 1986, p. 27. BiCMOS technology permits greater packing density, utilizes gates that operate at CMOS levels, and exhibits speeds that are becoming comparable to those of ECL-based systems.
Recent developments in integrated circuit fabrication technology have made it economically feasible to obtain the advantages of both ECL and CMOS technologies in a single circuit structure. Thus, high-performance BiCMOS structures are used in a variety of high density circuit applications such as, for example, static random access memory (SRAM). See, for example, R. A. Kertis et al, "A 12-ns ECL I/O 256K.times.1-bit SRAM Using a 1-.mu.m BiCMOS Technology," IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, October, 1988.
In a typical BiCMOS SRAM chip configuration, CMOS to low voltage level translation is inherent in the structure of the memory cell circuitry. The transistors in the memory cells produce output levels which are lower than those required for ECL operation. As described by Kertis et al., bipolar sense amplifiers are used to detect the low level output voltage and amplify it to ECL levels.
It would be desirable, however, to have available a translator circuit which converted CMOS levels to ECL levels for connection to external devices or for internal chip translation.